MAX17410GTM+【PDF 28/45 页】IC CTLR QPWM 2PH FOR IMV 48TQFN

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Dual-Phase, Quick-PWM Controller

for IMVP6+ CPU Core Power Supplies

Table 3. Operating Mode Truth Table (continued)

SHDN

INPUTS

DPRSTP DPRSLPVR

PSI

PHASE

OPERATION*

OPERATING MODE

Multiphase

High

X

Low

High

Forced-PWM

Nominal R TIME

Full Power. The no-load output voltage is determined by the

selected VID DAC code (D0 –D6, Table 4).

Slew Rate

1-Phase

Intermediate Power. The no-load output voltage is

High

X

Low

Low

Forced-PWM

Nominal R TIME

determined by the selected VID DAC code (D0 –D6, Table 4).

When PSI is pulled low, the MAX17410 immediately disables

Slew Rate

phase 2—DH2, and DL2 pulled low.

Deeper Sleep Mode. The no-load output voltage is

High

Low

High

X

1-Phase Pulse-

Skipping

Nominal R TIME

Slew Rate

determined by the selected VID DAC code (D0 –D6, Table 4).

When DPRSLPVR is pulled high, the MAX17410 immediately

enters 1-phase pulse-skipping operation allowing automatic

PWM/PFM switchover under light loads. The PWRGD and

CLKEN upper thresholds are blanked. DH2 and DL2 are

pulled low.

Deeper Sleep Slow Exit Mode. The no-load output voltage is

High

High

High

X

1-Phase Pulse-

Skipping

1/4th R TIME

Slew Rate

determined by the selected VID DAC code (D0 –D6, Table 4).

When DPRSTP is pulled high while DPRSLPVR is already

high, the MAX17410 remains in 1-phase pulse-skipping

operation allowing automatic PWM/PFM switchover under

light loads. The PWRGD and CLKEN upper thresholds are

blanked. DH2 and DL2 are pulled low.

Multiphase

Shutdown. When SHDN is pulled low, the MAX17410

immediately pulls PWRGD and PHASEGD low, CLKEN

Falling

X

X

X

Forced-PWM

1/8th R TIME

becomes high impedance, all enabled phases are activated,

and the output voltage is ramped down to ground. Once the

Slew Rate

output reaches 0V, the controller enters the low-power

shutdown state. See Figure 9.

Fault Mode. The fault latch has been set by the MAX17410

High

X

X

X

DISABLED

UVP or thermal-shutdown protection, or by the OVP

protection. The controller will remain in FAULT mode until

V CC power is cycled or SHDN toggled.

*Multiphase Operation = All enabled phases active.

X = Don’t care.

Table 4. IMVP6+ Output Voltage VID DAC Codes

OUTPUT

OUTPUT

D6

D5

D4

D3

D2

D1

D0

VOLTAGE

D6

D5

D4

D3

D2

D1

D0

VOLTAGE

(V)

(V)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

28

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